From: Ira Weiny <ira.we...@intel.com> The Flex Bus Port DVSEC was missing on type 3 devices which was blocking RAS checks.[1]
Add the Flex Bus Port DVSEC to type 3 devices as per CXL 3.0 8.2.1.3. [1] https://lore.kernel.org/linux-cxl/167096738875.2861540.11815053323626849940.st...@djiang5-desk3.ch.intel.com/ Cc: Dave Jiang <dave.ji...@intel.com> Cc: Jonathan Cameron <jonathan.came...@huawei.com> Cc: Ben Widawsky <bwida...@kernel.org> Cc: qemu-devel@nongnu.org Cc: linux-...@vger.kernel.org Signed-off-by: Ira Weiny <ira.we...@intel.com> Message-Id: <20221213-ira-flexbus-port-v2-1-eaa48d0e0...@intel.com> Reviewed-by: Michael S. Tsirkin <m...@redhat.com> Signed-off-by: Michael S. Tsirkin <m...@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.came...@huawei.com> --- hw/mem/cxl_type3.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 255590201a..dae4fd89ca 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -295,6 +295,17 @@ static void build_dvsecs(CXLType3Dev *ct3d) cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, GPF_DEVICE_DVSEC_LENGTH, GPF_DEVICE_DVSEC, GPF_DEVICE_DVSEC_REVID, dvsec); + + dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){ + .cap = 0x26, /* 68B, IO, Mem, non-MLD */ + .ctrl = 0x02, /* IO always enabled */ + .status = 0x26, /* same as capabilities */ + .rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */ + }; + cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, + PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0, + PCIE_FLEXBUS_PORT_DVSEC, + PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec); } static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) -- MST
