Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel On 12/20/22 01:23, Nicholas Miehlbradt wrote:
Implements the Dynamic Execution Control Register (DEXCR) and the Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction enable) and 6 (Privileged hash instruction enable) have architectural effects. Other aspects can be manipulated but have no effect on execution. Adds checks to these registers in the hashst and hashchk instructions so that they are executed as nops when not enabled. There is currently an RFC for the kernel interface for the DEXCR on the Linux PPC mailing list: https://lore.kernel.org/linuxppc-dev/20221128024458.46121-1-bg...@linux.ibm.com/ v3: - Fix typos v2: - Clearing of upper 32 bits of userspace registers is now performed on register read rather than register write. Nicholas Miehlbradt (2): target/ppc: Implement the DEXCR and HDEXCR target/ppc: Check DEXCR on hash{st, chk} instructions target/ppc/cpu.h | 19 +++++++++++++ target/ppc/cpu_init.c | 25 +++++++++++++++++ target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++----------- target/ppc/spr_common.h | 1 + target/ppc/translate.c | 19 +++++++++++++ 5 files changed, 107 insertions(+), 15 deletions(-)
