[PATCH] hw/riscv: Add support to change default RISCV hart memory region

[Vysakh P Pillai]

Add support to optionally specify a memory region container
to be used to override the default system memory used
by the the RISCV harts when they are realized. Additional
memory regions can be added as sub-regions of this container
to dynamically control the memory regions and mappings visible
from the hart.

Signed-off-by: Vysakh P Pillai <vysakhpil...@embeddedinn.xyz>
---
 hw/riscv/riscv_hart.c         | 5 +++++
 include/hw/riscv/riscv_hart.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 613ea2aaa0..7a8dcab7e7 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -33,6 +33,8 @@ static Property riscv_harts_props[] = {
     DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
     DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
                        DEFAULT_RSTVEC),
+    DEFINE_PROP_UINT64("cpu-memory", RISCVHartArrayState, 
+                       cpu_memory,NULL),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -49,6 +51,9 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int 
idx,
     qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
     s->harts[idx].env.mhartid = s->hartid_base + idx;
     qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
+    if (s->cpu_memory) {
+        object_property_set_link(OBJECT(&s->harts[idx].parent_obj), 
"memory",OBJECT(s->cpu_memory), &error_abort);
+    }
     return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
 }
 
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index bbc21cdc9a..3e5dfeeaae 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -38,6 +38,7 @@ struct RISCVHartArrayState {
     uint32_t hartid_base;
     char *cpu_type;
     uint64_t resetvec;
+    uint64_t cpu_memory;
     RISCVCPU *harts;
 };
 
-- 
2.34.1