On Thu, Nov 24, 2022 at 10:00 PM Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> Convert the riscv CPU class to use 3-phase reset, so it doesn't
> need to use device_class_set_parent_reset() any more.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 4 ++--
> target/riscv/cpu.c | 12 ++++++++----
> 2 files changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a9e25053f8..443d15a47c0 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -395,7 +395,7 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass,
> RISCV_CPU)
> /**
> * RISCVCPUClass:
> * @parent_realize: The parent class' realize handler.
> - * @parent_reset: The parent class' reset handler.
> + * @parent_phases: The parent class' reset phase handlers.
> *
> * A RISCV CPU model.
> */
> @@ -404,7 +404,7 @@ struct RISCVCPUClass {
> CPUClass parent_class;
> /*< public >*/
> DeviceRealize parent_realize;
> - DeviceReset parent_reset;
> + ResettablePhases parent_phases;
> };
>
> struct RISCVCPUConfig {
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d14e95c9dc1..6fe176e4833 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -519,18 +519,20 @@ static void riscv_restore_state_to_opc(CPUState *cs,
> env->bins = data[1];
> }
>
> -static void riscv_cpu_reset(DeviceState *dev)
> +static void riscv_cpu_reset_hold(Object *obj)
> {
> #ifndef CONFIG_USER_ONLY
> uint8_t iprio;
> int i, irq, rdzero;
> #endif
> - CPUState *cs = CPU(dev);
> + CPUState *cs = CPU(obj);
> RISCVCPU *cpu = RISCV_CPU(cs);
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> CPURISCVState *env = &cpu->env;
>
> - mcc->parent_reset(dev);
> + if (mcc->parent_phases.hold) {
> + mcc->parent_phases.hold(obj);
> + }
> #ifndef CONFIG_USER_ONLY
> env->misa_mxl = env->misa_mxl_max;
> env->priv = PRV_M;
> @@ -1161,11 +1163,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> CPUClass *cc = CPU_CLASS(c);
> DeviceClass *dc = DEVICE_CLASS(c);
> + ResettableClass *rc = RESETTABLE_CLASS(c);
>
> device_class_set_parent_realize(dc, riscv_cpu_realize,
> &mcc->parent_realize);
>
> - device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
> + resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
> + &mcc->parent_phases);
>
> cc->class_by_name = riscv_cpu_class_by_name;
> cc->has_work = riscv_cpu_has_work;
> --
> 2.25.1
>
>
