On Fri, Nov 18, 2022 at 10:44 PM Weiwei Li <liwei...@iscas.ac.cn> wrote: > > Add encode and trans* functions support for Zcb instructions > > Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/insn16.decode | 24 ++++++ > target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++++++++++++++++++++++ > target/riscv/translate.c | 2 + > 3 files changed, 126 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > > diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode > index b62664b6af..47603ec1e0 100644 > --- a/target/riscv/insn16.decode > +++ b/target/riscv/insn16.decode > @@ -43,6 +43,8 @@ > %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 > %imm_lui 12:s1 2:5 !function=ex_shift_12 > > +%zcb_b_uimm 5:1 6:1 > +%zcb_h_uimm 5:1 !function=ex_shift_1 > > # Argument sets imported from insn32.decode: > &empty !extern > @@ -53,6 +55,7 @@ > &b imm rs2 rs1 !extern > &u imm rd !extern > &shift shamt rs1 rd !extern > +&r2 rd rs1 !extern > > > # Formats 16: > @@ -89,6 +92,13 @@ > > @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 > > +@zcb_unary ... ... ... .. ... .. &r2 rs1=%rs1_3 > rd=%rs1_3 > +@zcb_binary ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 > rd=%rs1_3 > +@zcb_lb ... . .. ... .. ... .. &i imm=%zcb_b_uimm rs1=%rs1_3 > rd=%rs2_3 > +@zcb_lh ... . .. ... .. ... .. &i imm=%zcb_h_uimm rs1=%rs1_3 > rd=%rs2_3 > +@zcb_sb ... . .. ... .. ... .. &s imm=%zcb_b_uimm rs1=%rs1_3 > rs2=%rs2_3 > +@zcb_sh ... . .. ... .. ... .. &s imm=%zcb_h_uimm rs1=%rs1_3 > rs2=%rs2_3 > + > # *** RV32/64C Standard Extension (Quadrant 0) *** > { > # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. > @@ -180,3 +190,17 @@ sw 110 . ..... ..... 10 @c_swsp > sd 111 . ..... ..... 10 @c_sdsp > c_fsw 111 . ..... ..... 10 @c_swsp > } > + > +# *** RV64 and RV32 Zcb Extension *** > +c_zext_b 100 111 ... 11 000 01 @zcb_unary > +c_sext_b 100 111 ... 11 001 01 @zcb_unary > +c_zext_h 100 111 ... 11 010 01 @zcb_unary > +c_sext_h 100 111 ... 11 011 01 @zcb_unary > +c_zext_w 100 111 ... 11 100 01 @zcb_unary > +c_not 100 111 ... 11 101 01 @zcb_unary > +c_mul 100 111 ... 10 ... 01 @zcb_binary > +c_lbu 100 000 ... .. ... 00 @zcb_lb > +c_lhu 100 001 ... 0. ... 00 @zcb_lh > +c_lh 100 001 ... 1. ... 00 @zcb_lh > +c_sb 100 010 ... .. ... 00 @zcb_sb > +c_sh 100 011 ... 0. ... 00 @zcb_sh > diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc > b/target/riscv/insn_trans/trans_rvzce.c.inc > new file mode 100644 > index 0000000000..de96c4afaf > --- /dev/null > +++ b/target/riscv/insn_trans/trans_rvzce.c.inc > @@ -0,0 +1,100 @@ > +/* > + * RISC-V translation routines for the Zcb Standard Extension. > + * > + * Copyright (c) 2021-2022 PLCT Lab > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along > with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + */ > + > +#define REQUIRE_ZCB(ctx) do { \ > + if (!ctx->cfg_ptr->ext_zcb) \ > + return false; \ > +} while (0) > + > +static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl); > +} > + > +static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a) > +{ > + REQUIRE_ZCB(ctx); > + REQUIRE_ZBB(ctx); > + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); > +} > + > +static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a) > +{ > + REQUIRE_ZCB(ctx); > + REQUIRE_ZBB(ctx); > + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl); > +} > + > +static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a) > +{ > + REQUIRE_ZCB(ctx); > + REQUIRE_ZBB(ctx); > + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl); > +} > + > +static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a) > +{ > + REQUIRE_64BIT(ctx); > + REQUIRE_ZCB(ctx); > + REQUIRE_ZBA(ctx); > + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl); > +} > + > +static bool trans_c_not(DisasContext *ctx, arg_c_not *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl); > +} > + > +static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a) > +{ > + REQUIRE_ZCB(ctx); > + REQUIRE_M_OR_ZMMUL(ctx); > + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); > +} > + > +static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_load(ctx, a, MO_UB); > +} > + > +static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_load(ctx, a, MO_UW); > +} > + > +static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_load(ctx, a, MO_SW); > +} > + > +static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_store(ctx, a, MO_UB); > +} > + > +static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) > +{ > + REQUIRE_ZCB(ctx); > + return gen_store(ctx, a, MO_UW); > +} > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index ee24b451e3..ca01da3309 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -1069,6 +1069,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, > target_ulong pc) > > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > +#include "insn_trans/trans_rvzce.c.inc" > + > /* Include decoders for factored-out extensions */ > #include "decode-XVentanaCondOps.c.inc" > > -- > 2.25.1 > >