From: Alex Bennée <alex.ben...@linaro.org>
a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
this for the CPU interface register. The fact we don't implement it
shows up when running Xen with -d guest_error which is definitely
wrong because the guest is perfectly entitled to read it.
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
hw/intc/arm_gic.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1a04144c38b..7a34bc0998a 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -973,8 +973,18 @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset,
MemTxAttrs attrs)
/* GICD_TYPER byte 1 */
return (s->security_extn << 2);
}
- if (offset < 0x08)
+ if (offset == 8) {
+ /* GICD_IIDR byte 0 */
+ return 0x3b; /* Arm JEP106 identity */
+ }
+ if (offset == 9) {
+ /* GICD_IIDR byte 1 */
+ return 0x04; /* Arm JEP106 identity */
+ }
+ if (offset < 0x0c) {
+ /* All other bytes in this range are RAZ */
return 0;
+ }
if (offset >= 0x80) {
/* Interrupt Group Registers: these RAZ/WI if this is an NS
* access to a GIC with the security extensions, or if the GIC
--
2.25.1
