From: Pavel Dovgalyuk <pavel.dovgal...@ispras.ru>
This patch changes condition and function name for enabling
indexed load instructions for Octeon vCPUs. Octeons do not
have DSP extension, but implement LBX-and-others.
Signed-off-by: Pavel Dovgalyuk <pavel.dovgal...@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
target/mips/tcg/translate.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 2f2d707a12..4c4bd0823d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -12173,12 +12173,16 @@ enum {
#include "nanomips_translate.c.inc"
/* MIPSDSP functions. */
-static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
- int rd, int base, int offset)
+
+/* Indexed load is not for DSP only */
+static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
+ int rd, int base, int offset)
{
TCGv t0;
- check_dsp(ctx);
+ if (!(ctx->insn_flags & INSN_OCTEON)) {
+ check_dsp(ctx);
+ }
t0 = tcg_temp_new();
if (base == 0) {
@@ -14523,7 +14527,7 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_LBUX:
case OPC_LHX:
case OPC_LWX:
- gen_mipsdsp_ld(ctx, op2, rd, rs, rt);
+ gen_mips_lx(ctx, op2, rd, rs, rt);
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");
--
2.38.1
