On 11/5/22 06:26, Taylor Simpson wrote:
Direct block chaining is documented here https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chainingHexagon inner loops end with the endloop0 instruction To go back to the beginning of the loop, this instructions writes to PC from register SA0 (start address 0). To use direct block chaining, we have to assign PC with a constant value. So, we specialize the code generation when the start of the translation block is equal to SA0. When this is the case, we defer the compare/branch from endloop0 to gen_end_tb. When this is done, we can assign the start address of the TB to PC. Signed-off-by: Taylor Simpson <tsimp...@quicinc.com> --- target/hexagon/cpu.h | 17 ++++++++---- target/hexagon/gen_tcg.h | 3 ++ target/hexagon/translate.h | 1 + target/hexagon/genptr.c | 57 ++++++++++++++++++++++++++++++++++++++ target/hexagon/translate.c | 34 +++++++++++++++++++++++ 5 files changed, 107 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index ff8c26272d..5260e0f127 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -152,16 +152,23 @@ struct ArchCPU {#include "cpu_bits.h" +typedef union {+ uint32_t i; + struct { + bool is_tight_loop:1; + }; +} HexStateFlags;
I don't see this as an improvement on manual flags handling, as it makes the flags value be dependent on host bit-field ordering. This makes it more difficult to compare traces across hosts.
Otherwise, Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
