We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.
Signed-off-by: Rui Wang <wang...@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
.../loongarch/insn_trans/trans_farith.c.inc | 36 +++++++++++++++++++
target/loongarch/insn_trans/trans_fcmp.c.inc | 5 +++
.../loongarch/insn_trans/trans_fmemory.c.inc | 16 +++++++++
target/loongarch/insn_trans/trans_fmov.c.inc | 20 +++++++++++
target/loongarch/translate.c | 4 +++
target/loongarch/translate.h | 1 +
7 files changed, 84 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 49393d95d8..abe4a819b2 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -48,6 +48,7 @@ static const char * const excp_names[] = {
[EXCCODE_BRK] = "Break",
[EXCCODE_INE] = "Instruction Non-Existent",
[EXCCODE_IPE] = "Instruction privilege error",
+ [EXCCODE_FPD] = "Floating Point Disabled",
[EXCCODE_FPE] = "Floating Point Exception",
[EXCCODE_DBP] = "Debug breakpoint",
[EXCCODE_BCE] = "Bound Check Exception",
@@ -184,6 +185,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_BRK:
case EXCCODE_INE:
case EXCCODE_IPE:
+ case EXCCODE_FPD:
case EXCCODE_FPE:
case EXCCODE_BCE:
env->CSR_BADV = env->pc;
diff --git a/target/loongarch/insn_trans/trans_farith.c.inc
b/target/loongarch/insn_trans/trans_farith.c.inc
index 7bb3f41aee..3574b9b746 100644
--- a/target/loongarch/insn_trans/trans_farith.c.inc
+++ b/target/loongarch/insn_trans/trans_farith.c.inc
@@ -3,9 +3,28 @@
* Copyright (c) 2021 Loongson Technology Corporation Limited
*/
+static void check_fpe(DisasContext *ctx)
+{
+#ifndef CONFIG_USER_ONLY
+ TCGLabel *skip = gen_new_label();
+ TCGv tmp = tcg_temp_new();
+
+ tcg_gen_andi_tl(tmp, cpu_euen, R_CSR_EUEN_FPE_MASK);
+ tcg_gen_brcond_tl(TCG_COND_NE, tmp, ctx->zero, skip);
+ tcg_temp_free(tmp);
+
+ generate_exception(ctx, EXCCODE_FPD);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+
+ gen_set_label(skip);
+#endif
+}
+
static bool gen_fff(DisasContext *ctx, arg_fff *a,
void (*func)(TCGv, TCGv_env, TCGv, TCGv))
{
+ check_fpe(ctx);
+
func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]);
return true;
}
@@ -13,6 +32,8 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a,
static bool gen_ff(DisasContext *ctx, arg_ff *a,
void (*func)(TCGv, TCGv_env, TCGv))
{
+ check_fpe(ctx);
+
func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]);
return true;
}
@@ -22,6 +43,9 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
int flag)
{
TCGv_i32 tflag = tcg_constant_i32(flag);
+
+ check_fpe(ctx);
+
func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj],
cpu_fpr[a->fk], cpu_fpr[a->fa], tflag);
return true;
@@ -29,18 +53,24 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
{
+ check_fpe(ctx);
+
tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 31);
return true;
}
static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
{
+ check_fpe(ctx);
+
tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 63);
return true;
}
static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
{
+ check_fpe(ctx);
+
tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31));
gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
return true;
@@ -48,12 +78,16 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
{
+ check_fpe(ctx);
+
tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63));
return true;
}
static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
{
+ check_fpe(ctx);
+
tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000);
gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
return true;
@@ -61,6 +95,8 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
{
+ check_fpe(ctx);
+
tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL);
return true;
}
diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc
b/target/loongarch/insn_trans/trans_fcmp.c.inc
index 93a6a2230f..32b903231b 100644
--- a/target/loongarch/insn_trans/trans_fcmp.c.inc
+++ b/target/loongarch/insn_trans/trans_fcmp.c.inc
@@ -29,6 +29,8 @@ static bool trans_fcmp_cond_s(DisasContext *ctx,
arg_fcmp_cond_s *a)
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+ check_fpe(ctx);
+
fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
flags = get_fcmp_flags(a->fcond >> 1);
@@ -44,6 +46,9 @@ static bool trans_fcmp_cond_d(DisasContext *ctx,
arg_fcmp_cond_d *a)
TCGv var = tcg_temp_new();
uint32_t flags;
void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+
+ check_fpe(ctx);
+
fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
flags = get_fcmp_flags(a->fcond >> 1);
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc
b/target/loongarch/insn_trans/trans_fmemory.c.inc
index 74ee98f63a..508af75adf 100644
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -15,6 +15,8 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp
mop)
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;
+ check_fpe(ctx);
+
if (a->imm) {
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
@@ -36,6 +38,8 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a,
MemOp mop)
TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
TCGv temp = NULL;
+ check_fpe(ctx);
+
if (a->imm) {
temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
@@ -56,6 +60,8 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp
mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv addr = tcg_temp_new();
+ check_fpe(ctx);
+
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
@@ -70,6 +76,8 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp
mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv addr = tcg_temp_new();
+ check_fpe(ctx);
+
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
tcg_temp_free(addr);
@@ -83,6 +91,8 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp
mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv addr = tcg_temp_new();
+ check_fpe(ctx);
+
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -98,6 +108,8 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a,
MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv addr = tcg_temp_new();
+ check_fpe(ctx);
+
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -112,6 +124,8 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,
MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv addr = tcg_temp_new();
+ check_fpe(ctx);
+
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
@@ -127,6 +141,8 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a,
MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
TCGv addr = tcg_temp_new();
+ check_fpe(ctx);
+
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc
b/target/loongarch/insn_trans/trans_fmov.c.inc
index 5537e3dd35..a1d87719f8 100644
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
@@ -12,6 +12,8 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
TCGv zero = tcg_constant_tl(0);
TCGv cond = tcg_temp_new();
+ check_fpe(ctx);
+
tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca]));
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero,
cpu_fpr[a->fj], cpu_fpr[a->fk]);
@@ -26,6 +28,8 @@ static bool gen_f2f(DisasContext *ctx, arg_ff *a,
TCGv dest = cpu_fpr[a->fd];
TCGv src = cpu_fpr[a->fj];
+ check_fpe(ctx);
+
func(dest, src);
if (nanbox) {
gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
@@ -39,6 +43,8 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,
{
TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
+ check_fpe(ctx);
+
func(cpu_fpr[a->fd], src);
return true;
}
@@ -48,6 +54,8 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ check_fpe(ctx);
+
func(dest, cpu_fpr[a->fj]);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -59,6 +67,8 @@ static bool trans_movgr2fcsr(DisasContext *ctx,
arg_movgr2fcsr *a)
uint32_t mask = fcsr_mask[a->fcsrd];
TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE);
+ check_fpe(ctx);
+
if (mask == UINT32_MAX) {
tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0));
} else {
@@ -90,6 +100,8 @@ static bool trans_movfcsr2gr(DisasContext *ctx,
arg_movfcsr2gr *a)
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ check_fpe(ctx);
+
tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));
tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -116,6 +128,8 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf
*a)
{
TCGv t0 = tcg_temp_new();
+ check_fpe(ctx);
+
tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
tcg_temp_free(t0);
@@ -125,6 +139,8 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf
*a)
static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)
{
+ check_fpe(ctx);
+
tcg_gen_ld8u_tl(cpu_fpr[a->fd], cpu_env,
offsetof(CPULoongArchState, cf[a->cj & 0x7]));
return true;
@@ -134,6 +150,8 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf
*a)
{
TCGv t0 = tcg_temp_new();
+ check_fpe(ctx);
+
tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
tcg_temp_free(t0);
@@ -143,6 +161,8 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf
*a)
static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
{
+ check_fpe(ctx);
+
tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,
offsetof(CPULoongArchState, cf[a->cj & 0x7]));
return true;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 6091772349..5204653701 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -18,11 +18,13 @@
#include "fpu/softfloat.h"
#include "translate.h"
#include "internals.h"
+#include "cpu-csr.h"
/* Global register indices */
TCGv cpu_gpr[32], cpu_pc;
static TCGv cpu_lladdr, cpu_llval;
TCGv_i64 cpu_fpr[32];
+TCGv_i64 cpu_euen;
#include "exec/gen-icount.h"
@@ -267,6 +269,8 @@ void loongarch_translate_init(void)
}
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc),
"pc");
+ cpu_euen = tcg_global_mem_new(cpu_env,
+ offsetof(CPULoongArchState, CSR_EUEN), "cpu_euen");
cpu_lladdr = tcg_global_mem_new(cpu_env,
offsetof(CPULoongArchState, lladdr), "lladdr");
cpu_llval = tcg_global_mem_new(cpu_env,
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 9cc12512d1..3bf68867f5 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -41,5 +41,6 @@ void generate_exception(DisasContext *ctx, int excp);
extern TCGv cpu_gpr[32], cpu_pc;
extern TCGv_i32 cpu_fscr0;
extern TCGv_i64 cpu_fpr[32];
+extern TCGv_i64 cpu_euen;
#endif
--
2.38.1
