Hi Alistair,
>> RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
> Newline here
>> + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_AON_WDT_IRQ));
> and here please
I've deleted the public create function and added newlines in patch v2.
Thank you for the review !
Regards,
Tommy
On Mon, Oct 10, 2022 at 10:27 AM Alistair Francis <alistai...@gmail.com>
wrote:
> On Thu, Sep 22, 2022 at 6:45 PM Tommy Wu <tommy...@sifive.com> wrote:
> >
> > Create the AON device when we realize the sifive_e machine.
> > This patch only implemented the functionality of the watchdog timer,
> > not all the functionality of the AON device.
> >
> > Signed-off-by: Tommy Wu <tommy...@sifive.com>
> > ---
> > hw/riscv/Kconfig | 1 +
> > hw/riscv/sifive_e.c | 5 +++--
> > include/hw/riscv/sifive_e.h | 7 ++++---
> > 3 files changed, 8 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> > index 79ff61c464..50890b1b75 100644
> > --- a/hw/riscv/Kconfig
> > +++ b/hw/riscv/Kconfig
> > @@ -59,6 +59,7 @@ config SIFIVE_E
> > select SIFIVE_PLIC
> > select SIFIVE_UART
> > select SIFIVE_E_PRCI
> > + select SIFIVE_E_AON
> > select UNIMP
> >
> > config SIFIVE_U
> > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> > index d65d2fd869..f9c05cfd3a 100644
> > --- a/hw/riscv/sifive_e.c
> > +++ b/hw/riscv/sifive_e.c
> > @@ -45,6 +45,7 @@
> > #include "hw/intc/riscv_aclint.h"
> > #include "hw/intc/sifive_plic.h"
> > #include "hw/misc/sifive_e_prci.h"
> > +#include "hw/misc/sifive_e_aon.h"
> > #include "chardev/char.h"
> > #include "sysemu/sysemu.h"
> >
> > @@ -222,8 +223,8 @@ static void sifive_e_soc_realize(DeviceState *dev,
> Error **errp)
> > RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
> > RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
> > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
>
> Newline here
>
> > - create_unimplemented_device("riscv.sifive.e.aon",
> > - memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
> > + sifive_e_aon_create(sys_mem, memmap[SIFIVE_E_DEV_AON].base,
> > + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_AON_WDT_IRQ));
>
> and here please
>
> Otherwise:
>
> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
>
> Alistair
>
> > sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
> >
> > /* GPIO */
> > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> > index 83604da805..7de2221564 100644
> > --- a/include/hw/riscv/sifive_e.h
> > +++ b/include/hw/riscv/sifive_e.h
> > @@ -75,9 +75,10 @@ enum {
> > };
> >
> > enum {
> > - SIFIVE_E_UART0_IRQ = 3,
> > - SIFIVE_E_UART1_IRQ = 4,
> > - SIFIVE_E_GPIO0_IRQ0 = 8
> > + SIFIVE_E_AON_WDT_IRQ = 1,
> > + SIFIVE_E_UART0_IRQ = 3,
> > + SIFIVE_E_UART1_IRQ = 4,
> > + SIFIVE_E_GPIO0_IRQ0 = 8
> > };
> >
> > #define SIFIVE_E_PLIC_HART_CONFIG "M"
> > --
> > 2.27.0
> >
> >
>
