Instantiate the L2 cache controller on the ARM devboards which have one,
since we have a dummy model of it now. Note that the only non-MP board
with an L2x0 is the PB1176, which we don't model.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
This is intended to be applied after the l2x0 implementation patch,
obviously.
hw/realview.c | 2 ++
hw/vexpress.c | 1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/realview.c b/hw/realview.c
index 750a279..fe75b03 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -223,6 +223,8 @@ static void realview_init(ram_addr_t ram_size,
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
}
+ sysbus_create_varargs("l2x0", realview_binfo.smp_priv_base + 0x2000,
+ NULL);
} else {
uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
/* For now just create the nIRQ GIC, and ignore the others. */
diff --git a/hw/vexpress.c b/hw/vexpress.c
index 08c93d5..b8d69bb 100644
--- a/hw/vexpress.c
+++ b/hw/vexpress.c
@@ -176,6 +176,7 @@ static void vexpress_a9_init(ram_addr_t ram_size,
/* 0x100ec000 TrustZone Address Space Controller */
/* 0x10200000 CoreSight debug APB */
/* 0x1e00a000 PL310 L2 Cache Controller */
+ sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
/* CS0: NOR0 flash : 0x40000000 .. 0x44000000 */
/* CS4: NOR1 flash : 0x44000000 .. 0x48000000 */
--
1.7.1
