On Fri, Sep 30, 2022 at 11:28 AM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension
> Add check for these properties
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 24 ++++++++++++++++++++++++
> target/riscv/cpu.h | 6 ++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b29c88b9f0..7da3de1725 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -782,6 +782,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> }
>
> + if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> + error_setg(errp, "Zcf is only relevant to RV32");
> + return;
> + }
> +
> + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
> + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
> + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt require Zca extension");
> + return;
> + }
> +
> + if ((((env->misa_ext & RVD) && (env->misa_ext & RVC)) ||
> + cpu->cfg.ext_zcd) && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
> + error_setg(errp,
> + "Zcmp/Zcmt are incompatible with Zcd, which is "
> + "included when C and D extensions are both present");
> + return;
> + }
> +
> + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
> + error_setg(errp, "Zcmt extension requires Zicsr");
> + return;
> + }
> +
> if (cpu->cfg.ext_zk) {
> cpu->cfg.ext_zkn = true;
> cpu->cfg.ext_zkr = true;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index b131fa8c8e..db3eca1d8a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -428,6 +428,12 @@ struct RISCVCPUConfig {
> bool ext_zbkc;
> bool ext_zbkx;
> bool ext_zbs;
> + bool ext_zca;
> + bool ext_zcb;
> + bool ext_zcd;
> + bool ext_zcf;
> + bool ext_zcmp;
> + bool ext_zcmt;
> bool ext_zk;
> bool ext_zkn;
> bool ext_zknd;
> --
> 2.25.1
>
>
