On 10/18/22 01:27, LIU Zhiwei wrote:
Maybe I can run RISU on qemu-aarch64(x86) and qemu-aarch64(risc-v) to check the RISC-V
backend.
This is a good start for debugging a tcg backend. It's not comprehensive, because RISU
executes one instruction at a time then raises an exception to check the results. This
means that the tcg optimizer doesn't have much to work with, which means that the tcg
backend is not as stressed as it could be.
I've long wanted to have the ability to have TCG unit tests where a
virtual processor could be defined for the purpose of directly
exercising TCG.
We already have many ISAs as the front end of TCG. Will the virtual processor
here be some
different?
It wouldn't. This is my argument against creating a new virtual processor.
I do think we should be better about creating regression tests for bugs fixed, in the form
of small focused assembly test cases which get run via check-tcg.
r~
