On Wed, Oct 12, 2022 at 11:15 AM Alistair Francis <alistair.fran...@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.fran...@wdc.com> > > Since commit 4047368938f6 "accel/tcg: Introduce tlb_set_page_full" we > have been seeing this assert > > ../accel/tcg/cputlb.c:1294: tlb_set_page_with_attrs: Assertion > `is_power_of_2(size)' failed. > > When running Tock on the OpenTitan machine. > > The issue is that pmp_get_tlb_size() would return a TLB size that wasn't > a power of 2. The size was also smaller then TARGET_PAGE_SIZE. > > This patch ensures that any TLB size less then TARGET_PAGE_SIZE is > rounded down to 1 to ensure it's a valid size. > > Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
Thanks! Applied to riscv-to-apply.next Alistair > --- > This is based on advice from Richard: > https://patchwork.kernel.org/project/qemu-devel/patch/20221004141051.110653-9-richard.hender...@linaro.org/#25043166 > > target/riscv/pmp.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index ea2b67d947..2b43e399b8 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -628,6 +628,18 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr > tlb_sa, > } > > if (*tlb_size != 0) { > + /* > + * At this point we have a tlb_size that is the smallest possible > size > + * That fits within a TARGET_PAGE_SIZE and the PMP region. > + * > + * If the size is less then TARGET_PAGE_SIZE we drop the size to 1. > + * This means the result isn't cached in the TLB and is only used for > + * a single translation. > + */ > + if (*tlb_size < TARGET_PAGE_SIZE) { > + *tlb_size = 1; > + } > + > return true; > } > > -- > 2.37.3 >
