On Mon, 3 Oct 2022 at 15:57, Jerome Forissier
<jerome.foriss...@linaro.org> wrote:
>
> According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
> SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
> is advertised. This has to be taken care of when QEMU boots directly
> into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
> Link: [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
Ooh, that detailed set of control bit requirements is new
since I last read that doc -- we should probably go through
and cross-check that we're setting them all correctly.
> Signed-off-by: Jerome Forissier <jerome.foriss...@linaro.org>
> ---
> hw/arm/boot.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index ada2717f76..ee3858b673 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -763,6 +763,10 @@ static void do_cpu_reset(void *opaque)
> if (cpu_isar_feature(aa64_sve, cpu)) {
> env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
> }
> + if (cpu_isar_feature(aa64_sme, cpu)) {
> + env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
> + env->cp15.scr_el3 |= SCR_ENTP2;
> + }
The doc also says that we (as fake EL3) should be setting
SMCR_EL3.LEN to the same value for all CPUs. Currently we do
do that, but it's always the reset value of 0. Richard: does
that have any odd effects (I have a feeling it clamps the
VL to the minimum supported value)? Should we be setting
SMCR_EL3.LEN to the max supported value here ?
thanks
-- PMM
