On 10/8/22 08:36, Richard Henderson wrote:
Intel has now given guarantees about the atomicity of SSE read
and write instructions on cpus supporting AVX. We can use these
instead of the much slower cmpxchg16b.
Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
Paolo, we probably ought to modify gen_ld[oy]_env_A0 to match,
at least with CF_PARALLEL set.
Or, rather, just gen_ldo/sto.
Curiously, there are no guarantees at all for
vmovdqa mem, %ymmN
r~
