Reviewing the interrupt rework patch series, Fabiano noted[1] that the POWER8 User's Manual lists the Directed Hypervisor Doorbell interrupt, even without implementing the "Embedded.Processor Control" category. The manual also lists the msgclr and msgsnd instructions, but the decode legacy code currently gates them with the PPC2_PRCNTL flag, which is not enabled for this CPU.
Reading the Power ISA v2.07, we noticed that the title of the Processor Control chapter does not include the category information like in Power ISA v2.06, and the instruction listing in the appendices says that their category is "S\nE.PC". The document is not clear about this notation, but since implementations should support only one environment (embedded or server), I'd interpret this change as "these instructions are now available if the processor implements the server environment or E.PC category." While reviewing the flag for those instructions, we also saw that the msgsync, introduced in PowerISA v3.0, was available on all processors with the PPC2_PRCNTL flag, which includes older CPUs like e500mc and e6500. This patch series fixes the instruction flags for these three instructions. We then take this opportunity to move processor control instruction to decodetree, fixing an embarrassing error in the definition of the REQUIRE_HV macro along the way. [1] https://lists.gnu.org/archive/html/qemu-ppc/2022-09/msg00586.html Matheus Ferst (6): target/ppc: fix msgclr/msgsnd insns flags target/ppc: fix msgsync insns flags target/ppc: fix REQUIRE_HV macro definition target/ppc: move msgclr/msgsnd to decodetree target/ppc: move msgclrp/msgsndp to decodetree target/ppc: move msgsync to decodetree target/ppc/insn32.decode | 8 ++ target/ppc/translate.c | 86 ++------------- .../ppc/translate/processor-ctrl-impl.c.inc | 103 ++++++++++++++++++ 3 files changed, 119 insertions(+), 78 deletions(-) create mode 100644 target/ppc/translate/processor-ctrl-impl.c.inc -- 2.25.1
