On 10/6/22 08:46, Peter Maydell wrote:
Side note, looks like we didn't update vttbr_write() to know about the EL2&0 MMU indexes ?
EL2&0 is a single-stage regime, unaffected by VTTBR. r~
On 10/6/22 08:46, Peter Maydell wrote:
Side note, looks like we didn't update vttbr_write() to know about the EL2&0 MMU indexes ?
EL2&0 is a single-stage regime, unaffected by VTTBR. r~