From: Alistair Francis <alistair.fran...@wdc.com> The following changes since commit 6160d8ff81fb9fba70f5dad88d43ffd0fa44984c:
Merge tag 'edgar/xilinx-next-2022-09-21.for-upstream' of https://github.com/edgarigl/qemu into staging (2022-09-22 13:24:28 -0400) are available in the Git repository at: g...@github.com:alistair23/qemu.git pull-riscv-to-apply-20220923-2 for you to fetch changes up to a4260684f8e2c8722d1feae0d41d956fc4109007: hw/riscv/sifive_e: Fix inheritance of SiFiveEState (2022-09-23 09:11:34 +1000) ---------------------------------------------------------------- Second RISC-V PR for QEMU 7.2 * Fixup typos and register addresses for Ibex SPI * Cleanup the RISC-V virt machine documentation * Remove the sideleg and sedeleg CSR macros * Fix the CSR check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} * Remove fixed numbering from GDB xml feature files * Allow setting the resetvec for the OpenTitan machine * Check the correct exception cause in vector GDB stub * Fix inheritance of SiFiveEState ---------------------------------------------------------------- Alex Bennée (1): docs/system: clean up code escape for riscv virt platform Alistair Francis (3): target/riscv: Set the CPU resetvec directly hw/riscv: opentitan: Fixup resetvec hw/riscv: opentitan: Expose the resetvec as a SoC property Andrew Burgess (2): target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml target/riscv: remove fixed numbering from GDB xml feature files Bernhard Beschow (1): hw/riscv/sifive_e: Fix inheritance of SiFiveEState Frank Chang (1): target/riscv: Check the correct exception cause in vector GDB stub Rahul Pathak (1): target/riscv: Remove sideleg and sedeleg Weiwei Li (1): target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Wilfred Mallawa (2): hw/ssi: ibex_spi: fixup typos in ibex_spi_host hw/ssi: ibex_spi: update reg addr docs/system/riscv/virt.rst | 13 +++++++++---- include/hw/riscv/opentitan.h | 2 ++ include/hw/riscv/sifive_e.h | 3 ++- target/riscv/cpu.h | 3 +-- target/riscv/cpu_bits.h | 2 -- disas/riscv.c | 2 -- hw/riscv/opentitan.c | 8 +++++++- hw/ssi/ibex_spi_host.c | 8 ++++---- target/riscv/cpu.c | 13 +++---------- target/riscv/csr.c | 13 +++++++++---- target/riscv/gdbstub.c | 36 ++++-------------------------------- target/riscv/machine.c | 6 +++--- gdb-xml/riscv-32bit-cpu.xml | 6 +----- gdb-xml/riscv-32bit-fpu.xml | 10 +--------- gdb-xml/riscv-64bit-cpu.xml | 6 +----- gdb-xml/riscv-64bit-fpu.xml | 10 +--------- 16 files changed, 48 insertions(+), 93 deletions(-)
