On Sun, Sep 18, 2022 at 6:29 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> After RISCVException enum is introduced, riscv_csrrw_debug() returns
> RISCV_EXCP_NONE to indicate there's no error. RISC-V vector GDB stub
> should check the result against RISCV_EXCP_NONE instead of value 0.
> Otherwise, 'E14' packet would be incorrectly reported for vector CSRs
> when using "info reg vector" GDB command.
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Jim Shu <jim....@sifive.com>
> Reviewed-by: Tommy Wu <tommy...@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/gdbstub.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 9ed049c29e..118bd40f10 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -211,7 +211,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env,
> GByteArray *buf, int n)
> target_ulong val = 0;
> int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return gdb_get_regl(buf, val);
> }
>
> @@ -238,7 +238,7 @@ static int riscv_gdb_set_vector(CPURISCVState *env,
> uint8_t *mem_buf, int n)
> target_ulong val = ldtul_p(mem_buf);
> int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
>
> - if (result == 0) {
> + if (result == RISCV_EXCP_NONE) {
> return sizeof(target_ulong);
> }
>
> --
> 2.36.1
>
>
