On 12/22/2011 04:30 PM, Peter Maydell wrote:
On 22 December 2011 07:03, Evgeny Voevodin<e.voevo...@samsung.com> wrote:
Second GIC (external) is represented as "exynos4210.gic" with splitted
mapping for CPU (0x10480000) and Distributer (0x10490000) (we used
arm_gic.c availability to split CPU and Distributer memories).
The reason for creation of this device with it's own read/write functions
is:
CPU and Distributer registers which are banked per SMP Core in internal GIC
are not banked in external GIC and their offsets could not be used as is
with arm_gic.c.
External GIC registers in comparison to Internal GIC registers are moved
from base by offset n * 0x8000 for each SMP Core, where n is SMP Core index.
Right, so just map each of the memory regions arm_gic exposes for
core 0, core 1, ... to these addresses, and don't map the memory
region corresponding to "CPU interface for this core" at all.
-- PMM
Do you mean to use s->gic.cpuiomem[NCPU+1] as in a9mpcore.c
a9mp_priv_init() done?
What should we use if we need the same for distributor which is
represented as gic.iomem?
Extend distributor in the same way?
--
Kind regards,
Evgeny Voevodin,
Leading Software Engineer,
ASWG, Moscow R&D center, Samsung Electronics
e-mail: e.voevo...@samsung.com
