On Tue, Aug 23, 2022 at 4:55 AM Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> The riscv target incorrectly enabled semihosting always, whether the
> user asked for it or not. Call semihosting_enabled() passing the
> correct value to the is_userspace argument, which fixes this and also
> handles the userspace=on argument. Because we do this at translate
> time, we no longer need to check the privilege level in
> riscv_cpu_do_interrupt().
>
> Note that this is a behaviour change: we used to default to
> semihosting being enabled, and now the user must pass
> "-semihosting-config enable=on" if they want it.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 9 +++------
> target/riscv/translate.c | 1 +
> target/riscv/insn_trans/trans_privileged.c.inc | 3 ++-
> 3 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 59b3680b1b2..2b84febf275 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1342,12 +1342,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong mtval2 = 0;
>
> if (cause == RISCV_EXCP_SEMIHOST) {
> - if (env->priv >= PRV_S) {
> - do_common_semihosting(cs);
> - env->pc += 4;
> - return;
> - }
> - cause = RISCV_EXCP_BREAKPOINT;
> + do_common_semihosting(cs);
> + env->pc += 4;
> + return;
> }
>
> if (!async) {
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 63b04e8a948..f9e6258ec5d 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -28,6 +28,7 @@
>
> #include "exec/translator.h"
> #include "exec/log.h"
> +#include "semihosting/semihost.h"
>
> #include "instmap.h"
> #include "internals.h"
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index 46f96ad74d4..3281408a874 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -52,7 +52,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
> * that no exception will be raised when fetching them.
> */
>
> - if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
> + if (semihosting_enabled(ctx->mem_idx < PRV_S) &&
> + (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) {
> pre = opcode_at(&ctx->base, pre_addr);
> ebreak = opcode_at(&ctx->base, ebreak_addr);
> post = opcode_at(&ctx->base, post_addr);
> --
> 2.25.1
>
>
