On 11/8/22 22:41, Furquan Shaikh wrote:
Unlike ARM, RISC-V does not define a separate breakpoint type for semihosting. Instead, it is entirely ABI. Thus, we need an option to allow users to configure what the ebreak behavior should be for different privilege levels - M, S, U, VS, VU. As per the RISC-V privilege specification[1], ebreak traps into the execution environment. However, RISC-V debug specification[2] provides ebreak{m,s,u,vs,vu} configuration bits to allow ebreak behavior to be configured to trap into debug mode instead. This change adds settable properties for RISC-V CPUs - `ebreakm`, `ebreaks`, `ebreaku`, `ebreakvs` and `ebreakvu` to allow user to configure whether qemu should treat ebreak as semihosting traps or trap according to the privilege specification.[1] https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-privileged.pdf [2] https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf Signed-off-by: Furquan Shaikh <furq...@rivosinc.com> --- target/riscv/cpu.c | 8 ++++++++ target/riscv/cpu.h | 7 +++++++ target/riscv/cpu_helper.c | 26 +++++++++++++++++++++++++- 3 files changed, 40 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
