Also, initialize only one RAM bank. The second bank is a dummy one
(zero size) which is here to match the hard coded number of banks in
ppc405ep_init(). We will adjust this number when ppc4xx_sdram_init()
can be called directly, after we have replaced ppc405ep_init().
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
hw/ppc/ppc405.h | 17 +++++++++++++++
hw/ppc/ppc405_boards.c | 29 +++++++++++--------------
hw/ppc/ppc405_uc.c | 49 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 78 insertions(+), 17 deletions(-)
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index 83f156f585c8..c8cddb71733a 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -25,6 +25,7 @@
#ifndef PPC405_H
#define PPC405_H
+#include "qom/object.h"
#include "hw/ppc/ppc4xx.h"
#define PPC405EP_SDRAM_BASE 0x00000000
@@ -62,6 +63,22 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
+#define TYPE_PPC405_SOC "ppc405-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
+
+struct Ppc405SoCState {
+ /* Private */
+ DeviceState parent_obj;
+
+ /* Public */
+ MemoryRegion sram;
+ MemoryRegion ram_memories[2];
+ hwaddr ram_bases[2], ram_sizes[2];
+
+ MemoryRegion *dram_mr;
+ hwaddr ram_size;
+};
+
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 24ec948d22a4..96db52c5a309 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -54,6 +54,8 @@ struct Ppc405MachineState {
/* Private */
MachineState parent_obj;
/* Public */
+
+ Ppc405SoCState soc;
};
#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
@@ -232,12 +234,10 @@ static void boot_from_kernel(MachineState *machine,
PowerPCCPU *cpu)
static void ppc405_init(MachineState *machine)
{
+ Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
PowerPCCPU *cpu;
- MemoryRegion *sram = g_new(MemoryRegion, 1);
- MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
- hwaddr ram_bases[2], ram_sizes[2];
MemoryRegion *sysmem = get_system_memory();
DeviceState *uicdev;
@@ -248,23 +248,18 @@ static void ppc405_init(MachineState *machine)
exit(EXIT_FAILURE);
}
- /* XXX: fix this */
- memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias",
- machine->ram, 0, machine->ram_size);
- ram_bases[0] = 0;
- ram_sizes[0] = machine->ram_size;
- memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
- ram_bases[1] = 0x00000000;
- ram_sizes[1] = 0x00000000;
+ object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
+ TYPE_PPC405_SOC);
+ object_property_set_uint(OBJECT(&ppc405->soc), "ram-size",
+ machine->ram_size, &error_fatal);
+ object_property_set_link(OBJECT(&ppc405->soc), "dram",
+ OBJECT(machine->ram), &error_abort);
+ qdev_realize(DEVICE(&ppc405->soc), NULL, &error_abort);
- cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
+ cpu = ppc405ep_init(sysmem, ppc405->soc.ram_memories,
ppc405->soc.ram_bases,
+ ppc405->soc.ram_sizes,
33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
- /* allocate SRAM */
- memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE,
- &error_fatal);
- memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram);
-
/* allocate and load BIOS */
if (machine->firmware) {
MemoryRegion *bios = g_new(MemoryRegion, 1);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index d6420c88d3a6..7033bac6bf3f 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -30,6 +30,7 @@
#include "hw/ppc/ppc.h"
#include "hw/i2c/ppc4xx_i2c.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "ppc405.h"
#include "hw/char/serial.h"
#include "qemu/timer.h"
@@ -1530,3 +1531,51 @@ PowerPCCPU *ppc405ep_init(MemoryRegion
*address_space_mem,
return cpu;
}
+
+static void ppc405_soc_realize(DeviceState *dev, Error **errp)
+{
+ Ppc405SoCState *s = PPC405_SOC(dev);
+ Error *err = NULL;
+
+ memory_region_init_alias(&s->ram_memories[0], OBJECT(s),
+ "ppc405.ram.alias", s->dram_mr, 0, s->ram_size);
+ s->ram_bases[0] = 0;
+ s->ram_sizes[0] = s->ram_size;
+
+ /* allocate SRAM */
+ memory_region_init_ram(&s->sram, OBJECT(s), "ppc405.sram",
+ PPC405EP_SRAM_SIZE, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE,
+ &s->sram);
+}
+
+static Property ppc405_soc_properties[] = {
+ DEFINE_PROP_LINK("dram", Ppc405SoCState, dram_mr, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+ DEFINE_PROP_UINT64("ram-size", Ppc405SoCState, ram_size, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_soc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = ppc405_soc_realize;
+ dc->user_creatable = false;
