On Mon, Jun 20, 2022 at 5:05 PM ~eopxd <eo...@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.c...@sifive.com>
>
> Signed-off-by: eop Chen <eop.c...@sifive.com>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>
> Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
> target/riscv/vector_helper.c | 11 +++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 8ce3d28603..c1bd29329e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3275,6 +3275,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
> \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> data = \
> FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
> vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
> cpu_env, s->cfg_ptr->vlen / 8, \
> @@ -3313,6 +3314,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m
> *a)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> static gen_helper_gvec_3_ptr * const fns[4] = {
> gen_helper_viota_m_b, gen_helper_viota_m_h,
> gen_helper_viota_m_w, gen_helper_viota_m_d,
> @@ -3343,6 +3345,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> static gen_helper_gvec_2_ptr * const fns[4] = {
> gen_helper_vid_v_b, gen_helper_vid_v_h,
> gen_helper_vid_v_w, gen_helper_vid_v_d,
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 315742c6b8..52518648bb 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4879,11 +4879,16 @@ static void vmsetm(void *vd, void *v0, void *vs2,
> CPURISCVState *env,
> uint32_t vl = env->vl;
> uint32_t total_elems = env_archcpu(env)->cfg.vlen;
> uint32_t vta_all_1s = vext_vta_all_1s(desc);
> + uint32_t vma = vext_vma(desc);
> int i;
> bool first_mask_bit = false;
>
> for (i = env->vstart; i < vl; i++) {
> if (!vm && !vext_elem_mask(v0, i)) {
> + /* set masked-off elements to 1s */
> + if (vma) {
> + vext_set_elem_mask(vd, i, 1);
> + }
> continue;
> }
> /* write a zero to all following active elements */
> @@ -4944,11 +4949,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2,
> CPURISCVState *env, \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t sum = 0; \
> int i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> *((ETYPE *)vd + H(i)) = sum; \
> @@ -4975,10 +4983,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState
> *env, uint32_t desc) \
> uint32_t esz = sizeof(ETYPE); \
> uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> uint32_t vta = vext_vta(desc); \
> + uint32_t vma = vext_vma(desc); \
> int i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); \
> continue; \
> } \
> *((ETYPE *)vd + H(i)) = i; \
> --
> 2.34.2
>
>
