On Mon, 20 Jun 2022 at 19:13, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> These SME instructions are nominally within the SVE decode space,
> so we add them to sve.decode and translate-sve.c.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/translate-a64.h | 1 +
> target/arm/sve.decode | 5 ++++-
> target/arm/translate-a64.c | 15 +++++++++++++++
> target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++++++++++
> 4 files changed, 58 insertions(+), 1 deletion(-)
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 62b5f3040c..13bdd027a5 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -1286,6 +1286,19 @@ static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
> return true;
> }
>
> +static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL *a)
> +{
> + if (!dc_isar_feature(aa64_sme, s)) {
> + return false;
> + }
> + if (sme_enabled_check(s)) {
> + TCGv_i64 rd = cpu_reg_sp(s, a->rd);
> + TCGv_i64 rn = cpu_reg_sp(s, a->rn);
> + tcg_gen_addi_i64(rd, rn, a->imm * s->svl);
> + }
> + return true;
> +}
> +
> static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
> {
> if (!dc_isar_feature(aa64_sve, s)) {
> @@ -1299,6 +1312,19 @@ static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
> return true;
> }
>
> +static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL *a)
> +{
> + if (!dc_isar_feature(aa64_sme, s)) {
> + return false;
> + }
> + if (sme_enabled_check(s)) {
> + TCGv_i64 rd = cpu_reg_sp(s, a->rd);
> + TCGv_i64 rn = cpu_reg_sp(s, a->rn);
> + tcg_gen_addi_i64(rd, rn, a->imm * (s->svl / 8));
> + }
> + return true;
> +}
> +
> static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
> {
> if (!dc_isar_feature(aa64_sve, s)) {
> @@ -1311,6 +1337,18 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
> return true;
> }
>
> +static bool trans_RDSVL(DisasContext *s, arg_RDSVL *a)
> +{
> + if (!dc_isar_feature(aa64_sme, s)) {
> + return false;
> + }
> + if (sme_enabled_check(s)) {
> + TCGv_i64 reg = cpu_reg(s, a->rd);
> + tcg_gen_movi_i64(reg, a->imm * s->svl);
> + }
> + return true;
> +}
I think we should define functions that parallel the SVE
vec_full_reg_size() and pred_full_reg_size() rather than directly
looking at s->svl, for consistency with how we did the SVE code.
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
