On Fri, Jun 10, 2022 at 1:14 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> Introduce build_tdata1() to build tdata1 register content, which can be
> shared among all types of triggers.
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> ---
> target/riscv/debug.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index abbcd38a17..089aae0696 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -94,18 +94,23 @@ static inline target_ulong get_trigger_type(CPURISCVState
> *env,
> return extract_trigger_type(env, tdata1);
> }
>
> -static inline target_ulong trigger_type(CPURISCVState *env,
> - trigger_type_t type)
> +static inline target_ulong build_tdata1(CPURISCVState *env,
> + trigger_type_t type,
> + bool dmode, target_ulong data)
> {
> target_ulong tdata1;
>
> switch (riscv_cpu_mxl(env)) {
> case MXL_RV32:
> - tdata1 = RV32_TYPE(type);
> + tdata1 = RV32_TYPE(type) |
> + (dmode ? RV32_DMODE : 0) |
> + (data & RV32_DATA_MASK);
RV32_DATA_MASK should be introduced in this patch
> break;
> case MXL_RV64:
> case MXL_RV128:
> - tdata1 = RV64_TYPE(type);
> + tdata1 = RV64_TYPE(type) |
> + (dmode ? RV64_DMODE : 0) |
> + (data & RV64_DATA_MASK);
ditto
> break;
> default:
> g_assert_not_reached();
> @@ -490,7 +495,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
> CPUWatchpoint *wp)
>
> void riscv_trigger_init(CPURISCVState *env)
> {
> - target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
> + target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
> int i;
>
> /* init to type 2 triggers */
> --
>
Otherwise,
Reviewed-by: Bin Meng <bmeng...@gmail.com>
