From: Dragan Mladjenovic <dragan.mladjeno...@syrmia.com>
If both rs and rt are the same register, the nanoMIPS instruction
BNEC[32] rs, rt, address is equivalent to NOP (branch is not taken and
there is no delay slot). This commit provides such behavior. Without
this commit, this scenario results in an incorrect behavior.
Signed-off-by: Dragan Mladjenovic <dragan.mladjeno...@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pe...@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Message-Id: <20220504110403.613168-5-stefan.pe...@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/tcg/nanomips_translate.c.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index 941cfaa6bb..1ee5c8c8d4 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -4528,7 +4528,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
switch (extract32(ctx->opcode, 14, 2)) {
case NM_BNEC:
check_nms(ctx);
- gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
+ if (rs == rt) {
+ /* NOP */
+ ctx->hflags |= MIPS_HFLAG_FBNSLOT;
+ } else {
+ gen_compute_branch_nm(ctx, OPC_BNE, 4, rs, rt, s);
+ }
break;
case NM_BLTC:
if (rs != 0 && rt != 0 && rs == rt) {
--
2.36.1
