On Thu, 2 Jun 2022 at 23:11, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This register is part of SME, but isn't closely related to the
> rest of the extension.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu.h | 1 +
> target/arm/helper.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 24c5266f35..245d144fa1 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -474,6 +474,7 @@ typedef struct CPUArchState {
> };
> uint64_t tpidr_el[4];
> };
> + uint64_t tpidr2_el0;
> /* The secure banks of these registers don't map anywhere */
> uint64_t tpidrurw_s;
> uint64_t tpidrprw_s;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 48534db0bd..204c5cf849 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -6283,6 +6283,35 @@ static const ARMCPRegInfo zcr_reginfo[] = {
> .writefn = zcr_write, .raw_writefn = raw_write },
> };
>
> +#ifdef TARGET_AARCH64
> +static CPAccessResult access_tpidr2(CPUARMState *env, const ARMCPRegInfo *ri,
> + bool isread)
> +{
> + int el = arm_current_el(env);
> +
> + if (el == 0) {
> + uint64_t sctlr = arm_sctlr(env, el);
> + if (!(sctlr & SCTLR_EnTP2)) {
> + uint64_t hcr = arm_hcr_el2_eff(env);
> + return hcr & HCR_TGE ? CP_ACCESS_TRAP_EL2 : CP_ACCESS_TRAP;
Do we really need to do this rather than just returning
CP_ACCESS_TRAP and letting the "take trap to EL2 if TGE
enabled" check in raise_exception() do the TGE routing?
> + }
> + }
> + if (el < 3
> + && arm_feature(env, ARM_FEATURE_EL3)
> + && !(env->cp15.scr_el3 & SCR_ENTP2)) {
> + return CP_ACCESS_TRAP_EL3;
> + }
> + return CP_ACCESS_OK;
> +}
thanks
-- PMM
