On Thu, Jun 2, 2022 at 3:32 AM <frederic.kon...@xilinx.com> wrote: > > From: Sai Pavan Boddu <sai.pavan.bo...@xilinx.com> > > Fix interrupt disable logic. Mask value 1 indicates that interrupts are > disabled. > > Signed-off-by: Sai Pavan Boddu <saip...@xilinx.com> > Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > Signed-off-by: Frederic Konrad <fkon...@amd.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > hw/display/xlnx_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c > index d0bea512bd..eed705219e 100644 > --- a/hw/display/xlnx_dp.c > +++ b/hw/display/xlnx_dp.c > @@ -889,7 +889,7 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, > uint64_t value, > xlnx_dp_update_irq(s); > break; > case DP_INT_DS: > - s->core_registers[DP_INT_MASK] |= ~value; > + s->core_registers[DP_INT_MASK] |= value; > xlnx_dp_update_irq(s); > break; > default: > -- > 2.25.1 > >
