On May 19 14:11, Lukasz Maniak wrote:
> On Tue, May 17, 2022 at 01:16:05PM +0200, Klaus Jensen wrote:
> > From: Klaus Jensen <k.jen...@samsung.com>
> >
> > The SRIOV series exposed an issued with how CC register writes are
> > handled and how CSTS is set in response to that. Specifically, after
> > applying the SRIOV series, the controller could end up in a state with
> > CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to
> > expect CSTS.RDY to transition to '1' but timing out.
> >
> > Clean this up.
> >
> > Signed-off-by: Klaus Jensen <k.jen...@samsung.com>
> > ---
> >
> > Note, this applies on top of nvme-next with v8 of Lukasz's sriov series.
> >
> > hw/nvme/ctrl.c | 35 +++++++++++------------------------
> > 1 file changed, 11 insertions(+), 24 deletions(-)
> >
> > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
> > index 658584d417fe..47d971b2404c 100644
> > --- a/hw/nvme/ctrl.c
> > +++ b/hw/nvme/ctrl.c
> > @@ -6190,9 +6190,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n,
> > NvmeResetType rst)
> >
> > if (pci_is_vf(pci_dev)) {
> > sctrl = nvme_sctrl(n);
> > +
> > stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED);
> > - } else {
> > - stl_le_p(&n->bar.csts, 0);
>
> Are you sure the registers do not need to be cleared for a reset type that
> does not involve a CC register i.e. FLR?
> Will these registers be zeroed out elsewhere during FLR?
> Indeed you are right. Posting a v2.
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