Signed-off-by: Víctor Colombo <victor.colo...@eldorado.org.br>
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/fp-impl.c.inc | 46 +++++++++++-------------------
target/ppc/translate/fp-ops.c.inc | 2 --
3 files changed, 20 insertions(+), 32 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2fbd4b2946..b7bd17e4d1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -91,6 +91,9 @@
@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc
rt=%x_frtp rb=%x_frbp
+&X_t rt
+@X_t ...... rt:5 ..... ..... .......... . &X_t
+
&X_tb rt rb
@X_tb ...... rt:5 ..... rb:5 .......... . &X_tb
@@ -320,6 +323,7 @@ SETNBCR 011111 ..... ..... ----- 0111100000 -
@X_bi
### Move To/From FPSCR
+MFFSCE 111111 ..... 00001 ----- 1001000111 - @X_t
MFFSCRN 111111 ..... 10110 ..... 1001000111 - @X_tb
MFFSCRNI 111111 ..... 10111 ---.. 1001000111 - @X_imm2
diff --git a/target/ppc/translate/fp-impl.c.inc
b/target/ppc/translate/fp-impl.c.inc
index 6872dbc185..531e8b8796 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -629,36 +629,6 @@ static void gen_mffsl(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
-/* mffsce */
-static void gen_mffsce(DisasContext *ctx)
-{
- TCGv_i64 t0;
- TCGv_i32 mask;
-
- if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) {
- return gen_mffs(ctx);
- }
-
- if (unlikely(!ctx->fpu_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_FPU);
- return;
- }
-
- t0 = tcg_temp_new_i64();
-
- gen_reset_fpstatus();
- tcg_gen_extu_tl_i64(t0, cpu_fpscr);
- set_fpr(rD(ctx->opcode), t0);
-
- /* Clear exception enable bits in the FPSCR. */
- tcg_gen_andi_i64(t0, t0, ~FP_ENABLES);
- mask = tcg_const_i32(0x0003);
- gen_helper_store_fpscr(cpu_env, t0, mask);
-
- tcg_temp_free_i32(mask);
- tcg_temp_free_i64(t0);
-}
-
static TCGv_i64 place_from_fpscr(int rt, uint64_t mask)
{
TCGv_i64 fpscr = tcg_temp_new_i64();
@@ -686,6 +656,22 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t
clear_mask,
tcg_temp_free_i64(fpscr_masked);
}
+static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a)
+{
+ TCGv_i64 fpscr;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_FPU(ctx);
+
+ gen_reset_fpstatus();
+ fpscr = place_from_fpscr(a->rt, UINT64_MAX);
+ store_fpscr_masked(fpscr, FP_ENABLES, tcg_constant_i64(0), 0x0003);
+
+ tcg_temp_free_i64(fpscr);
+
+ return true;
+}
+
static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb *a)
{
TCGv_i64 t1, fpscr;
diff --git a/target/ppc/translate/fp-ops.c.inc
b/target/ppc/translate/fp-ops.c.inc
index a5738fdb27..c4865da63f 100644
--- a/target/ppc/translate/fp-ops.c.inc
+++ b/target/ppc/translate/fp-ops.c.inc
@@ -76,8 +76,6 @@ GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE,
PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
-GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
- PPC2_ISA300),
GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
--
2.25.1
