> Thanks for looking up the a64fx register value. You don't need to > do anything more -- I'll fix up the TODO comment and put the right > value into this patch, either when I post a v2 of it or else when > I apply it to target-arm.next.
I understand. Thank you in advance. Shuuichirou. > -----Original Message----- > From: Peter Maydell <peter.mayd...@linaro.org> > Sent: Wednesday, May 18, 2022 7:31 PM > To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuic...@fujitsu.com> > Cc: Alex Bennée <alex.ben...@linaro.org>; Itaru Kitayama > <itaru.kitay...@gmail.com>; qemu-...@nongnu.org; qemu-devel@nongnu.org > Subject: Re: [PATCH] target/arm: Make number of counters in PMCR follow the > CPU > > On Wed, 18 May 2022 at 00:24, ishii.shuuic...@fujitsu.com > <ishii.shuuic...@fujitsu.com> wrote: > > > > Hi, Peter. > > > > > Shuuichirou, Itaru: this is another patch where we need to know > > > an A64FX register value... > > > > Sorry for the late reply. > > > > The initial value of the pmcr_el0 register in A64FX is 0x46014040. > > > > After applying this Peter's patch, should we submit a new patch as a64fx > > patch > from us? > > or do you want to fix your own modifications to the patch that peter has > > posted? > > Which is the best procedure? > > Thanks for looking up the a64fx register value. You don't need to > do anything more -- I'll fix up the TODO comment and put the right > value into this patch, either when I post a v2 of it or else when > I apply it to target-arm.next. > > -- PMM
