Le 30/04/2022 à 19:02, Richard Henderson a écrit :
Zero selects all cpu features in disas/m68k.c,
which is really what we want -- not limited to 68040.
But what happens when an instruction has to be decoded differently between 680x0 and
coldfire?
for instance in disas/m68k.c, we have:
{"addil", 6, one(0003200), one(0177700), "#l$s", m68000up },
{"addil", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
{"addl", 6, one(0003200), one(0177700), "#l$s", m68000up },
{"addl", 6, one(0003200), one(0177700), "#lDs", mcfisa_a },
{"andil", 6, one(0001200), one(0177700), "#l$s", m68000up },
{"andil", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
{"andl", 6, one(0001200), one(0177700), "#l$s", m68000up },
{"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a },
{"bchg", 4, one(0004100), one(0177700), "#b$s", m68000up },
{"bchg", 4, one(0004100), one(0177700), "#bqs", mcfisa_a },
{"bclr", 4, one(0004200), one(0177700), "#b$s", m68000up },
{"bclr", 4, one(0004200), one(0177700), "#bqs", mcfisa_a },
{"bset", 2, one(0000700), one(0170700), "Dd$s", m68000up | mcfisa_a },
{"bset", 2, one(0000700), one(0170700), "Ddvs", mcfisa_a },
{"bset", 4, one(0004300), one(0177700), "#b$s", m68000up },
{"bset", 4, one(0004300), one(0177700), "#bqs", mcfisa_a },
{"btst", 4, one(0004000), one(0177700), "#b@s", m68000up },
{"btst", 4, one(0004000), one(0177700), "#bqs", mcfisa_a },
{"cmpib", 4, one(0006000), one(0177700), "#b@s", m68000up },
{"cmpib", 4, one(0006000), one(0177700), "#bDs", mcfisa_b },
{"cmpiw", 4, one(0006100), one(0177700), "#w@s", m68000up },
{"cmpiw", 4, one(0006100), one(0177700), "#wDs", mcfisa_b },
{"cmpil", 6, one(0006200), one(0177700), "#l@s", m68000up },
{"cmpil", 6, one(0006200), one(0177700), "#lDs", mcfisa_a },
