On Thu, May 12, 2022 at 12:49 AM Anup Patel <apa...@ventanamicro.com> wrote:
>
> Currently, QEMU does not set hstatus.GVA bit for traps taken from
> HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
> on QEMU. This was working previously.
>
> This patch updates riscv_cpu_do_interrupt() to fix the above issue.
>
> Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
> Signed-off-by: Anup Patel <apa...@ventanamicro.com>Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index e1aa4f2097..b16bfe0182 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1367,7 +1367,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_INST_PAGE_FAULT: > case RISCV_EXCP_LOAD_PAGE_FAULT: > case RISCV_EXCP_STORE_PAGE_FAULT: > - write_gva = true; > + write_gva = env->two_stage_lookup; > tval = env->badaddr; > break; > case RISCV_EXCP_ILLEGAL_INST: > @@ -1434,7 +1434,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) > /* Trap into HS mode */ > env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false); > htval = env->guest_phys_fault_addr; > - write_gva = false; > } > env->hstatus = set_field(env->hstatus, HSTATUS_GVA, write_gva); > } > -- > 2.34.1 > >
