Hi Stefan,
On 4/5/22 13:03, Stefan Pejic wrote:
The field ac in nanoMips instruction MTHLIP rs, ac is specified in
nanoMips documentation as opcode[15..14] (2 bits). However, in the
current QEMU code, the corresponding argument passed to the helper
gen_helper_mthlip() has the value of opcode[15..11] (5 bits). Right
shift the value of this argument by three bits to fix this.
Indeed. This applies to all the class, so
gen_pool32axf_1_nanomips_insn() could directly take (shifted) 'ac'
argument instead of v2.
Anyhow:
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Stefan Pejic <stefan.pe...@syrmia.com>
---
target/mips/tcg/nanomips_translate.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index 916cece4d2..58ae35a156 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1597,7 +1597,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext
*ctx, uint32_t opc,
check_dsp(ctx);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_MTHLIP:
- tcg_gen_movi_tl(t0, v2);
+ tcg_gen_movi_tl(t0, v2 >> 3);
gen_helper_mthlip(t0, v0_t, cpu_env);
break;
case NM_SHILOV:
