Richard Henderson <richard.hender...@linaro.org> writes:
> On 4/20/22 12:42, Peter Maydell wrote: >> On Mon, 18 Apr 2022 at 20:19, Leandro Lupori >> <leandro.lup...@eldorado.org.br> wrote: >>> >>> PPC64 CPUs can change its endian dynamically, so semihosting code >>> must check its MSR at run time to determine if byte swapping is >>> needed. >> Arm CPUs also change endianness dynamically, so why is this >> change PPC-specific ? > > I'm reasonably certain that we simply don't test armbe or aarch64_be > semihosting. Leandro found this because qemu-system-ppc64 defaults to > BE and qemu-system-aarch64 defaults to LE. Maybe it is time to have a generic endianess variable in CPUState so we can avoid having arch specific hacks in the semihosting code. That said is endianess binary? I seem to recall on ARM the instruction stream is always in one endianess so it only really affects CPU data loads and stores. Is it the same for PPC? > > > r~ -- Alex Bennée
