On 4/18/22 17:22, Cédric Le Goater wrote:
On 4/18/22 21:10, Leandro Lupori wrote:
Add semihosting support for PPC64. This implementation is
based on the standard for ARM semihosting version 2.0, as
implemented by QEMU and documented in
https://github.com/ARM-software/abi-aa/releases
The PPC64 specific differences are the following:
Semihosting Trap Instruction: sc 7
Operation Number Register: r3
Parameter Register: r4
Return Register: r3
Data block field size: 64 bits
'sc' is a good way to implement semi hosting but we should make sure
that it is not colliding with future extensions, at least with the
next POWERPC processor. Is that the case ? if not, then the lev could
be reserved.
Power ISA 3.1B says that LEV values greater that 2 are reserved.
Level 2 is the ultravisor, so I assumed that level 7 was far enough from
current max level. I don't know if POWER11 will introduce new privilege
levels. Is this info publicly available somewhere? Or do you have a
better level in mind to use instead?
I think the part adding POWERPC_EXCP_SEMIHOST should be proposed in a
separate patch.
Ok, I can move it to a separate patch. That would be all changes in
target/ppc/cpu.h and target/ppc/excp_helper.c, right?
