On Thu, Apr 14, 2022 at 11:55 PM Niklas Cassel via <qemu-devel@nongnu.org> wrote: > > The device tree property "mmu-type" is currently exported as either > "riscv,sv32" or "riscv,sv48". > > However, the riscv cpu device tree binding [1] has a specific value > "riscv,none" for a HART without a MMU. > > Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu > option is disabled using rv32,mmu=off or rv64,mmu=off. > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17 > > Signed-off-by: Niklas Cassel <niklas.cas...@wdc.com> > --- > hw/riscv/virt.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) >
Reviewed-by: Bin Meng <bmeng...@gmail.com>
