On Wed, Mar 23, 2022 at 6:22 PM Weiwei Li <[email protected]> wrote: > > > 在 2022/3/23 下午7:13, Mayuresh Chitale 写道: > > Accesses to henvcfg, henvcfgh and senvcfg are allowed > > only if corresponding bit in mstateen0/hstateen0 is > > enabled. Otherwise an illegal instruction trap is > > generated. > > > > Signed-off-by: Mayuresh Chitale <[email protected]> > > --- > > target/riscv/csr.c | 82 ++++++++++++++++++++++++++++++++++++++++++---- > > 1 file changed, 76 insertions(+), 6 deletions(-) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 215c8ecef1..2388f0226f 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -39,6 +39,35 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations > > *ops) > > } > > > > /* Predicates */ > > +static RISCVException smstateen_acc_ok(CPURISCVState *env, int mode, int > > bit) > > +{ > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + bool virt = riscv_cpu_virt_enabled(env); > > + > > + if (!cpu->cfg.ext_smstateen) { > > + return RISCV_EXCP_NONE; > > + } > > + > > + if (!(env->mstateen[0] & 1UL << bit)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > I think here should be " & (1UL << bit) " . The same for following > similar cases.
Ok. Will fix it in the next version. > > Regards, > > Weiwei Li >
