On 25 November 2011 12:33, Gauresh Rane <gdr...@cs.ucla.edu> wrote: > Thanks for the reply. > The instruction that is causing problem is > 436: bx lr > > On single stepping and logging the trace I see that the lr has been set > correctly to jump back, in the beginning of the block and also the > microinstructions instructions generated match the following disassembly > of the elf.
What is the expected return address in LR ? (In particular, check that it has the low bit set to indicate a Thumb mode destination.) > Also all the registers which are pushed to the stack, > "r3, r4, r5, r6, r7, lr" are cleared to zero That is odd. I wonder if the processor is resetting for some reason. > After bx lr, pc becomes 0, it does not find any code there thus > throws a usage exception and runs Usage fault handler in a loop. (Actually the UsageFault when PC==0 is because it's trying to execute in the non-existent ARM mode.) > What do you mean by setting up the stack? Is it done seperately? I mean "setting SP to a value such that you can push registers without causing a memory fault". If you're not failing on the push instructions then you've probably got a valid stack. > Also I am not understanding where processor state values updated > in qemu code. All over the place. In particular for register value changes the generated code will include direct loads and stores to the bits of the CPUState structure containing registers. (Changes to PC are special too.) -- PMM
