On 3/13/22 04:55, Amir Gonnen wrote:
(Continue discussion from Re: [PATCH v4 24/33] target/nios2: Introduce shadow
register sets)
How does "cpu_crs_R" work?
... Otherwise, each gpr access would be indirect. I'm probably missing
something here.
They are indirect, but with some optimization.
Why not always access directly?
With an EIC each interrupt handler is associated with a specific shadow
register set, so we can expect that (on a sane use case) each block always
executes on the same register set.
If we update cpu_get_tb_cpu_state to translate differently based on STATUS.CRS
we would still end up with a single translation for each block.
This way the translator could emit direct registers access for shadow
registers, and we won't need to rely on optimizations to lower indirect access.
We could do that if we support fewer than 64 shadow register sets:
#define TCG_MAX_TEMPS 512
Global temps (e.g. cpu_R[]) count against that limit, and 64 * 32 == 2048.
The maximum number of shadow reg sets you could support like this would be
about 8.
r~
