Richard Henderson <richard.hender...@linaro.org> writes:
> The LDRD (register) instruction is UNPREDICTABLE if the Rm register > is the same as either Rt or Rt+1 (the two registers being loaded to). > We weren't making sure we avoided this, with the result that on some > host CPUs like the Cortex-A7 we would get a SIGILL because the CPU > chooses to UNDEF for this particular UNPREDICTABLE case. > > Since we've already checked that datalo is aligned, we can simplify > the test vs the Rm operand by aligning it before comparison. Check > for the two orderings before falling back to two ldr instructions. > > We don't bother to do anything similar for tcg_out_ldrd_rwb(), > because it is only used in tcg_out_tlb_read() with a fixed set of > registers which don't overlap. > > There is no equivalent UNPREDICTABLE case for STRD. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/896 > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> The fix looks sane to me (although I can't test because it seems my aarch32 on the SynQuacer does try it's best). So: Reviewed-by: Alex Bennée <alex.ben...@linaro.org> A wider question. Is this something that can be handled the constraints done by the register allocator? I assume that avoid direct aliasing if needed? -- Alex Bennée
