On 3/8/22 00:57, Peter Maydell wrote:
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
<richard.hender...@linaro.org> wrote:
Create an array of masks which detail the writable and readonly
bits for each control register. Apply them when writing to
control registers.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
What's the justification for this extra machinery? Does
existing guest code rely on writes to r/o bits being ignored ?
During review of a previous edition of this patch set, I asked myself: why isn't Amir
changing the shadow register set on WRCTL to STATUS, as the CRS field could change.
The answer is that the architecture disallows this, by making the CRS field read-only from
software. CRS can only be modified by interrupt entry and return.
Then I looked further and found more read-only fields, and lots of fields that are
reserved unless the appropriate cpu options are enabled. Again thining of CRS more so to
PRS when shadow register sets are *not* enabled -- we don't want software to put us into
some weird state.
I probably should have put all that in the patch description. :-)
r~
