On Fri, Feb 11, 2022 at 2:49 PM Weiwei Li <liwei...@iscas.ac.cn> wrote: > > This patchset implements RISC-V Float-Point in Integer Registers > extensions(Version 1.0), which includes Zfinx, Zdinx, Zhinx and Zhinxmin > extension. > > Specification: > https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0.pdf > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zfinx-upstream-v6 > > To test this implementation, specify cpu argument with 'zfinx > =true,zdinx=true,zhinx=true,zhinxmin=true' with > 'g=false,f=false,d=false,Zfh=false,Zfhmin=false' > This implementation can pass gcc tests, ci result can be found in > https://ci.rvperf.org/job/plct-qemu-zfinx-upstream/. > > v6: > * rename flags Z*inx to z*inx > * rebase on apply-to-riscv.next > > v5: > * put definition of ftemp and nftemp together, add comments for them > * sperate the declare of variable i from loop > > v4: > * combine register pair check for rv32 zdinx > * clear mstatus.FS when RVF is disabled by write_misa > > v3: > * delete unused reset for mstatus.FS > * use positive test for RVF instead of negative test for ZFINX > * replace get_ol with get_xl > * use tcg_gen_concat_tl_i64 to unify tcg_gen_concat_i32_i64 and > tcg_gen_deposit_i64 > > v2: > * hardwire mstatus.FS to zero when enable zfinx > * do register-pair check at the begin of translation > * optimize partial implemention as suggested > > Weiwei Li (6): > target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} > target/riscv: hardwire mstatus.FS to zero when enable zfinx > target/riscv: add support for zfinx > target/riscv: add support for zdinx > target/riscv: add support for zhinx/zhinxmin > target/riscv: expose zfinx, zdinx, zhinx{min} properties
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 17 ++ > target/riscv/cpu.h | 4 + > target/riscv/cpu_helper.c | 6 +- > target/riscv/csr.c | 25 +- > target/riscv/fpu_helper.c | 178 ++++++------ > target/riscv/helper.h | 4 +- > target/riscv/insn_trans/trans_rvd.c.inc | 285 ++++++++++++++----- > target/riscv/insn_trans/trans_rvf.c.inc | 314 +++++++++++++------- > target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- > target/riscv/internals.h | 32 ++- > target/riscv/translate.c | 149 +++++++++- > 11 files changed, 974 insertions(+), 372 deletions(-) > > -- > 2.17.1 > >
