On 2/23/22 12:31, David Miller wrote:
+#define F_EPI "stg %%r0, %[res] " : [res] "+m" (res) : : "r0", "r2", "r3"
+
+#define F_PRO asm ( \
+ "llihf %%r0,801\n" \
+ "lg %%r2, %[a]\n" \
+ "lg %%r3, %[b] " \
+ : : [a] "m" (a), \
+ [b] "m" (b) \
+ : "r2", "r3")
+
+#define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
+{ uint64_t res = 0; F_PRO; ASM; return res; }
+
+/* AND WITH COMPLEMENT */
+FbinOp(_ncrk, asm("ncrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_ncgrk, asm("ncgrk %%r0, %%r3, %%r2\n" F_EPI))
Better written as
asm("ncrk %0, %3, %2" : "=&r"(res) : "r"(a), "r"(b) : "cc");
and drop F_PRO and F_EPI. Use the asm constraints properly to place the
operands.
+/* NAND */
+FbinOp(_nnrk, asm("nnrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nngrk, asm("nngrk %%r0, %%r3, %%r2\n" F_EPI))
+
+/* NOT XOR */
+FbinOp(_nxrk, asm("nxrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nxgrk, asm("nxgrk %%r0, %%r3, %%r2\n" F_EPI))
+
+/* NOR */
+FbinOp(_nork, asm("nork %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nogrk, asm("nogrk %%r0, %%r3, %%r2\n" F_EPI))
+
+/* OR WITH COMPLEMENT */
+FbinOp(_ocrk, asm("ocrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_ocgrk, asm("ocgrk %%r0, %%r3, %%r2\n" F_EPI))
Similarly.
+++ b/tests/tcg/s390x/mie3-sel.c
@@ -0,0 +1,42 @@
+#include <stdint.h>
+
+
+#define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
+{ \
+uint64_t res = 0; \
+asm ( \
+ "lg %%r2, %[a]\n" \
+ "lg %%r3, %[b]\n" \
+ "lg %%r0, %[c]\n" \
+ "ltgr %%r0, %%r0\n" \
+ ASM \
+ "stg %%r0, %[res] " \
+ : [res] "=m" (res) \
+ : [a] "m" (a), \
+ [b] "m" (b), \
+ [c] "m" (c) \
+ : "r0", "r2", \
+ "r3", "r4" \
+ ); \
+ return res; \
+}
+
+
+Fi3 (_selre, "selre %%r0, %%r3, %%r2\n")
+Fi3 (_selgrz, "selgrz %%r0, %%r3, %%r2\n")
+Fi3 (_selfhrnz, "selfhrnz %%r0, %%r3, %%r2\n")
Similarly:
asm("ltgr %3, %3; selre %0, %2, %1"
: "=&r"(res) : "r"(a), "r"(b), "r"(c) : "cc");
Although none of this is going to work with .insn. We *ought* to be able to use the
debian11 update plus a change to tests/tcg/configure.sh to detect host support for
-march=z15 to drop that change.
r~
