Re: [PATCH 1/9] target/ppc: raise HV interrupts for partition table entry problems

[Cédric Le Goater]

On 2/15/22 04:16, Nicholas Piggin wrote:

Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.

Signed-off-by: Nicholas Piggin <npig...@gmail.com>

Adding the previous R-b for patchwork:

Reviewed-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb...@gmail.com>

C.

---
  target/ppc/mmu-radix64.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index d4e16bd7db..df2fec80ce 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -556,13 +556,13 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr 
eaddr,
      } else {
          if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
              if (guest_visible) {
-                ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
+                ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, 
DSISR_R_BADCONFIG);
              }
              return false;
          }
          if (!validate_pate(cpu, lpid, &pate)) {
              if (guest_visible) {
-                ppc_radix64_raise_si(cpu, access_type, eaddr, 
DSISR_R_BADCONFIG);
+                ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr, 
DSISR_R_BADCONFIG);
              }
              return false;
          }