On Jan 26 18:11, Lukasz Maniak wrote:
> From: Łukasz Gieryk <lukasz.gie...@linux.intel.com>
>
> An NVMe device with SR-IOV capability calculates the BAR size
> differently for PF and VF, so it makes sense to extract the common code
> to a separate function.
>
> Signed-off-by: Łukasz Gieryk <lukasz.gie...@linux.intel.com>
> ---
> hw/nvme/ctrl.c | 45 +++++++++++++++++++++++++++++++--------------
> 1 file changed, 31 insertions(+), 14 deletions(-)
>
> diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
> index 40eb6bd1a8..e101cb7d7c 100644
> --- a/hw/nvme/ctrl.c
> +++ b/hw/nvme/ctrl.c
> @@ -6431,6 +6431,34 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice
> *pci_dev)
> memory_region_set_enabled(&n->pmr.dev->mr, false);
> }
>
> +static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs,
> + unsigned *msix_table_offset,
> + unsigned *msix_pba_offset)
> +{
> + uint64_t bar_size, msix_table_size, msix_pba_size;
> +
> + bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE;
> + bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
> +
> + if (msix_table_offset) {
> + *msix_table_offset = bar_size;
> + }
> +
> + msix_table_size = PCI_MSIX_ENTRY_SIZE * total_irqs;
> + bar_size += msix_table_size;
> + bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
> +
> + if (msix_pba_offset) {
> + *msix_pba_offset = bar_size;
> + }
> +
> + msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8;
> + bar_size += msix_pba_size;
> +
> + bar_size = pow2ceil(bar_size);
> + return bar_size;
> +}
> +
> static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset,
> uint64_t bar_size)
> {
> @@ -6470,7 +6498,7 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev,
> uint8_t offset)
> static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
> {
> uint8_t *pci_conf = pci_dev->config;
> - uint64_t bar_size, msix_table_size, msix_pba_size;
> + uint64_t bar_size;
> unsigned msix_table_offset, msix_pba_offset;
> int ret;
>
> @@ -6496,19 +6524,8 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice
> *pci_dev, Error **errp)
> }
>
> /* add one to max_ioqpairs to account for the admin queue pair */
> - bar_size = sizeof(NvmeBar) +
> - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE;
> - bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
> - msix_table_offset = bar_size;
> - msix_table_size = PCI_MSIX_ENTRY_SIZE * n->params.msix_qsize;
> -
> - bar_size += msix_table_size;
> - bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB);
> - msix_pba_offset = bar_size;
> - msix_pba_size = QEMU_ALIGN_UP(n->params.msix_qsize, 64) / 8;
> -
> - bar_size += msix_pba_size;
> - bar_size = pow2ceil(bar_size);
> + bar_size = nvme_bar_size(n->params.max_ioqpairs + 1,
> n->params.msix_qsize,
> + &msix_table_offset, &msix_pba_offset);
>
> memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size);
> memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme",
> --
> 2.25.1
> Looks good, Reviewed-by: Klaus Jensen <k.jen...@samsung.com>
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