On Tue, 1 Feb 2022 at 23:15, Richard Petri <g...@rpls.de> wrote: > And if you still want to do a debug session: I think there is another > related problem. The `systick_reset` function sets the right clock > source, but I guess at the time of calling reset the `cpuclk` doesn't > have the right value (probably zero)? I was confused at first, because > the reset code suggests that everything is OK from the start, but that > doesn't seem to be the case. I don't have a good enough overview of the > qemu sources to know what is called when. But even if the reset would be > right, first setting the clock source and then en/disabling the timer is > the better order IMO.
Yeah, there is a bug here. On these boards there is no refclk, so the systick timer is supposed to say "refclk not connected, on reset we set SYST_CSR.CLOCKSOURCE to 1 (meaning use cpu clock) and make that bit read-only". But we weren't correctly detecting the lack of refclk so we were resetting to "use the refclk", which is bad because it has period 0, not being connected to anything. (If the guest explicitly programs the CLOCKSOURCE bit then it works around this bug, but in theory it shouldn't have to.) I'll send a patch in a moment. thanks -- PMM
