On Fri, Jan 28, 2022 at 7:06 PM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
> Reviewed-by: Anup Patel <a...@brainfault.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 5a1c0e239e..b820166dc5 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -641,6 +641,9 @@ restart:
> return TRANSLATE_FAIL;
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> /* Inner PTE, continue walking */
> + if (pte & (PTE_D | PTE_A | PTE_U)) {
> + return TRANSLATE_FAIL;
> + }
> base = ppn << PGSHIFT;
> } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
> /* Reserved leaf PTE flags: PTE_W */
> --
> 2.17.1
>
>
